Resistance is Futile! Building Better Wireload Models

Wireload models are like the weather. Many people talk about them, but not many people do anything about them! This paper will explore some of the myths and realities of wireload models: • why wireload models are important, and why nobody understands them • why your intuition is wrong • why you shouldn’t trust your silicon vendor • why floorplanning sometimes doesn’t matter • why having an accurate wireload model is a bad idea A technique for measuring the quality of wireload models will be described. Real-world results will be discussed. Cool graphics will be shown. A desperate plea for future work will be given. 1.0 Synthesis basics The typical methodology or flow used with Design Compiler is shown in Figure 1. Figure 1. Typical Flow The quality of the netlist is determined by: • synthesis tool (vendor and version) • technology library • RTL code • compile scripts and constraints • wireload model Much has been written on how to write better RTL code (“better” means the resulting netlist is smaller, faster, lower power, etc.). Also extensive work has been done on examining synthesis scripting styles and how to properly constrain your design. In contrast, very little has been said about wireload models. A wireload model is what the synthesis tool uses to estimate wire characteristics (e.g. interconnect delay) in the absence of physical layout data. For a wire with a given fanout, the wireload model specifies the capacitance, resistance, and area of the wire. (Here fanout is defined to be one less than the total number of pins on the net.) Although the synthesis tool has complete control over the netlist, the resulting timing is greatly affected by the physical layout. The wireload model is the only information that the synthesis tool has about the back-end place and route flow. Design Compiler library RTL code scripts & constraints wireload model